1. Field of the Invention
The present invention relates to a DRAM (dynamic random access memory) having multiple banks and a method for refreshing the data stored in the DRAM.
2. Background of the Invention
For DRAM, there is a refresh scheme in which row addresses are sequentially refreshed by updating them periodically using a refresh timer (RT) and a row address counter (RAC). There is also a RAS-Only-Refresh scheme (i.e., normal refresh). FIG. 1 illustrates a schematic diagram of a refresh scheme of the prior art. If there are multiple banks, RAC specifies a bank address R-bank and a row address R-row to be refreshed. The RAC sends a bank address R-bank to a bank selector (BS) and a row address, R-row to a row selector (RS). Another input to BS is a bank address (shown as Bank in FIG. 1) to be accessed. This address has been input to the address input (AI). A row address (shown as Row in FIG. 1) to be accessed, is input to RS from an address that has been input to AI.
BS outputs either the bank address R-bank or bank, while RS outputs either the row address R-row or row. Selection of a combination of the bank and row outputs or the R-bank and R-row outputs is specified by RT. RT comprises a timer circuit and specifies R-bank and R-row outputs at predetermined time intervals. The RT output is also input to a column enable (CE). A column address is input to CE from Al. CE temporarily stops column address output (i.e., column) where R-bank and R-row outputs are specified.
Either a bank, row address and column address to be accessed or a bank and row address to be refreshed are sent to a memory array. Since only one bank address and one row address can reside on their respective busses, only one bank and one row is accessible at any given time. Therefore, in spite of the fact that the remaining banks are not being accessed, they cannot be refreshed simultaneously. Because of the importance of maintaining data integrity, a refresh operation is generally placed at a higher priority level than other memory access functions and, therefore, memory availability and performance degrades.
It is therefore an object of the present invention to provide a DRAM that reduces access latency when refresh occurs.